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/* Copyright 1998 MLML - Moss Landing Marine Labs                             */
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/******************************************************************************/
/* Summary  : Routines to access Memory Mapped Latches & config Chip-Selects  */
/* Filename : IO_LATCH.C                                                      */
/* Author   : Luke Coletti                                                    */
/* Project  :                                                                 */
/* Version  : 1.0                                                             */
/* Compiler : Aztec C68k/ROM v5.2D                                            */
/* Created  : 07/15/99                                                        */
/* Archived :                                                                 */
/******************************************************************************/
/* Modification History:                                                      */
/*                                                                            */
/******************************************************************************/
#include        <TT8.h>                 /* Tattletale Model 8 Definitions */
#include        <tt8lib.h>              /* definitions and prototypes for Model 8 library */
#include        <sim332.h>
#include        <stdio.h>
#include        <math.h>
#include        "lobo.h"


extern uchar   modem_pwr;
extern ushort  WrLatch1Val;
extern ushort  WrLatch2Val;
extern ulong   CS0Base;
extern ulong   CS1Base;

void InitLatch_IO(void)
{
#asm
CSPAR0      equ     $FFFA44             ;Chip Select Pin Assignment Register 0
CSBAR0      equ     $FFFA4C             ;Chip Select 0 Base Address Register
CSOR0       equ     $FFFA4E             ;Chip Select 0 Option Register
CSBAR1      equ     $FFFA50             ;Chip Select 1 Base Address Register
CSOR1       equ     $FFFA52             ;Chip Select 1 Option Register

            move.w  CSPAR0,d0           ;get contents of CS Pin Assignment Reg 0
            andi.w  #$3FC3,d0           ;preserve states of CSBOOT & CS2-CS5
            ori.w   #$003C,d0           ;set CS0 (16-bit Port) CS1 (16-Bit Port)
            move.w  d0,CSPAR0           ;update CS Pin Assignment Reg 0

            move.w  #$4000,CSBAR0       ;set base of CS0 to 0x40,0000
            move.w  #$7C30,CSOR0        ;set option of CS0
            move.w  #$4008,CSBAR1       ;set base of CS1 to 0x40,0800
            move.w  #$7C30,CSOR1        ;set option of CS1

#endasm

    CS0Base  = BASEADDR(*CSBAR0);
    CS1Base  = BASEADDR(*CSBAR1);

    WrLatch1Val=0;
    WrLatch2Val=0;

    WrLatch2(WrLatch2Val);   /* clear Output Latch 2 */
    WrLatch1(WrLatch1Val);   /* clear Output Latch 1 */

    WrLatchDefaults();

}

void WrLatchDefaults(void)
{

//  Set_K1_K8_State( (RdLatch1() & 0xFF00) );   //open any closed relays
    Set_K1_K8_State(WR_LATCH1_DEFAULTS);
    Sleep(0);
    Sleep(250);

//  Set_K9_K11_State(K9_RESET);
    modem_pwr = FALSE;   //MODEM POWER is via Q8
    Set_Bit_WrLatch2(WR_LATCH2_DEFAULTS);
    Sleep(0);
    Sleep(250);

}

unsigned short RdLatch1(void)
{
#asm
RDLATCH1CS  equ     $400000             ;memory mapped input register, CS0
            move.w  RDLATCH1CS,d0       ;get contents of latch
                                        ;return from C function call
#endasm
}

void WrLatch1(unsigned short val)
{
;
#asm
WRLATCH1CS  equ     $400000             ;memory mapped output latch 1, CS0
            move.w  %%val,WRLATCH1CS    ;load contents into latch
                                        ;return from C function call
#endasm
}

void WrLatch2(unsigned short val)
{
;
#asm
WRLATCH2CS  equ     $400800             ;memory mapped output latch 2, CS1
            move.w  %%val,WRLATCH2CS    ;load contents into latch
                                        ;return from C function call
#endasm
}

unsigned short Set_K1_K8_State(unsigned short bitvals)
{

    WrLatch1(bitvals);
    Sleep(0);                   // 20ms coil activation time
    Sleep(TICKS_PER_SECOND/50); // should be plenty...
    WrLatch1(0);                // OK, you can stop now.

    return(RdLatch1() >> 8);

}

void Set_K9_K11_State(unsigned short bitvals)
{
unsigned short OnesComp;

    bitvals &= 0xFC00;          // don't mess with low Byte or Q6 & Q8 in this function
    OnesComp = ~bitvals;

    WrLatch2Val |= bitvals;
    WrLatch2(WrLatch2Val);
    Sleep(0);                   // 20ms coil activation time
    Sleep(TICKS_PER_SECOND/50); // should be plenty...
    WrLatch2Val &= OnesComp;    // let's see, where were we before?
    WrLatch2(WrLatch2Val);      // ahh, that's right!

    Sleep(0);
    Sleep(TICKS_PER_SECOND/2);  // 500ms debounce time
}

unsigned short Get_K1_K8_State(void)
{

    return(RdLatch1() >> 8);

}

void Set_Bit_WrLatch2(unsigned short bitvals)
{

    bitvals &= 0x03FF;          // don't mess with K9-K11 in this function

    WrLatch2Val |= bitvals;
    WrLatch2(WrLatch2Val);

}

void Clear_Bit_WrLatch2(unsigned short bitvals)
{
unsigned short OnesComp;

    bitvals &= 0x03FF;          // don't mess with K9-K11 in this function
    OnesComp = ~bitvals;

    WrLatch2Val &= OnesComp;
    WrLatch2(WrLatch2Val);

}